1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a structure for applying voltage stress between memory cells in a dynamic semiconductor memory device. More particularly, the invention relates to a structure for applying voltage stress between adjacent memory cell capacitors using a small number of signals.
2. Description of the Background Art
An acceleration test called burn-in test is performed for removing, from produced devices, any device having a short life time so as to ship the remaining ones. In this acceleration test, the produced devices are operated for a certain period of time under conditions severer than actual conditions in use, and any device having a short life time is broken. In other words, this acceleration test uses stress acceleration to reveal any potential defect which was not detected in a normal failure detection test.
Concerning a dynamic semiconductor memory device (hereinafter referred to as DRAM), the most important test is the burn-in test applied to memory cells accounting for a large percentage of elements on the device. However, with the remarkable increase in the storage capacity of the DRAM, only a small part of the total memory cells operates in one normal operating cycle of the DRAM. The number of memory cells connected to one word line is limited and the number of word lines selected in a normal operation at a time is determined by the refresh cycle. For example, in a 256M DRAM with 8K refresh cycle, only {fraction (1/8192)} (8K) of the total memory cells are selected in one normal operation cycle. In order to perform a burn-in test on all the memory cells, a memory cell row should be selected 8K times, which causes increase of time required for the burn-in test.
xe2x80x9c1996 Symposium on VLSI Circuits, Digest of Technical Papersxe2x80x9d discloses on pages 194 and 195, for example, a structure in which a greater number of word lines are selected simultaneously and accordingly a greater number of memory cells are selected than in a normal operation, in order to shorten the time required to do the burn-in test.
FIG. 25 is a schematic diagram illustrating a word line drive control unit disclosed in the document above. In FIG. 25, the word line drive control unit includes a block decoder 500 receiving test mode row decoder latch instruction signal TM_RDLTC and a row address signal RowAddr, a level shifter 501 boosting H level of an output signal of block decoder 500 to generate a block selection signal BLKSEL, a word line (WL) reset circuit 502 receiving test mode word line latch instruction signal TM_WLLTC, test mode word line reset instruction signal TM_WLRST and an internal row address strobe signal RAS, a level shifter 503 receiving a word line activation instruction signal WLON, a predecode signal X12 and a word line inactivation instruction signal WLOFF from WL reset circuit 502 to generate a word line activation timing signal and a word line reset timing signal, a buffer circuit 504 buffering the timing signals from level shifter 503 to generate a word line drive signal WLDV, and an NOR circuit 505 receiving the timing signals from level shifter 503 and word line drive signal WLDV from buffer circuit 504 to generate a word line reset signal WLRST.
When test mode row decoder latch instruction signal TM_RDLTC attains the active state, block decoder 500 maintains its set state without being reset regardless of the state of row address signal RowAddr, and fixes block selection signal BLKSEL at H level (when a memory block is selected).
In a normal operation mode, WL reset circuit 502 drives word line reset timing signal WLOFF into the active state according to internal row address strobe signal RAS. In a test mode, WL reset circuit 502 maintains word line reset timing signal WLOFF in the inactive state during the period in which test mode word line latch instruction signal TM_WLLTC is in the active state, and drives word line reset timing signal WLOFF into the active state when test mode word line reset instruction signal TM_WLRST is supplied.
Level shifter 503 receives word line activation timing signal WLON and predecode signal X12 to generate a word line drive timing signal in the active state according to word line activation timing signal WLON when predecode signal X12 is in the active state. Level shifter 503 maintains this state until word line reset timing signal WLOFF is activated.
NOR circuit 505 drives word line reset signal WLRST into the active state of H level when word line drive signal WLDV reaches the inactive state and an output signal of level shifter 503 attains L level. During the period in which word line drive signal WLDV is in the active state of H level, NOR circuit 505 maintains word line reset signal WLRST in the inactive state of L level.
The word line drive control unit further includes a decode circuit 506a corresponding to a word line WLi+1, being activated in response to activation of block selection signal BLKSEL from level shifter 501 and decoding predecode signals XAij and XAkl, a latch circuit 507a inverting and latching an output signal of decode circuit 506a, a word line drive circuit 508a transmitting word line drive signal WLDV to the associated word line WLi+1 when an output signal of latch circuit 507a is in the active state of L level, and a reset transistor 509a responsive to activation of word line reset signal WLRST for resetting word line WLi+1 to the ground voltage level.
Similarly, a decode circuit 506b activated in response to activation of block selection signal BLKSEL to decode predecode signals XAij and XAkl, a latch circuit 507b inverting and latching an output signal of decode circuit 506b, a word line drive circuit 508b transmitting word line drive signal WLDV to an associated word line WLi when an output signal of latch circuit 507b is in the active state of L level, and a reset transistor 509b which is turned on when word line reset signal WLRST is activated to reset word line WLi to the ground voltage level are provided corresponding to word line WLi.
Different combinations of predecode signals are respectively provided to decode circuits 506a and 506b. In a memory block selected by block selection signal BLKSEL, one word line is selected from a group of word lines selected by predecode signal X12 according to predecode signals XAij and XAkl. An operation in a test mode of the word line drive control unit shown in FIG. 25 is now described in conjunction with the signal waveform diagram illustrated in FIG. 26.
In the test mode, test mode instruction signal TM is first activated and simultaneously test mode row decoder latch instruction signal TM_RDLTC and test mode word line latch instruction signal TM_WLLTC are driven into the active state. Accordingly, block decoder 500 is set into a latching state and WL reset circuit 502 is set into a latching state.
In this test mode setting, word line activation timing signal WLON is in the inactive state, word line activation timing signal from level shifter 503 is at L level, word line drive signal WLDV is at L level, word line reset signal WLRST is at H level, and word lines WLi+1 and WLi are maintained at L level. Since no row address is supplied, block selection signal BLKSEL from level shifter 501 is at L level.
In this test mode, externally supplied row address strobe signal /RAS is driven into the active state of L level and simultaneously a row address signal is supplied. According to the row address signal, block decoder 500 is selected, an output signal of block decoder 500 rises to H level, and the H level is latched according to test mode row decoder latch instruction signal TM_RDLTC. Thus, block selection signal BLKSEL from level shifter 501 is fixed at H level in this test mode period. Block selection signal BLKSEL is fixed at H level and decode circuits 506a and 506b are activated.
According to externally supplied row address strobe signal /RAS, internal row address strobe signal RAS is activated and accordingly word line drive timing signal WLON is activated. According to the supplied row address signal, predecode signals XAij, XAkl and X12 are generated and a designated word line (word line WL1 in FIG. 26) is driven into the selected state. Remaining word lines are in the non-selected state.
External row address strobe signal /RAS is temporarily set in the inactive state. At this time, internal row address strobe signal RAS is also inactivated. However, in response to activation of test mode word line latch instruction signal TM_WLLTC, WL reset circuit 502 maintains word line reset timing signal WLOFF in the inactive state. A timing signal from level shifter 503 thus maintains H level and selected word line WL1 maintains the selected state.
Externally supplied row address strobe signal /RAS is driven into the active state again, and another row address is supplied to drive another word line into the selected state. When the another word line WL2 is driven into the selected state, previously selected word line WL1 maintains its selected state. Subsequently, external row address strobe signal /RAS is toggled and a row address is simultaneously supplied so that a plurality of word lines are driven simultaneously into the selected state.
With the plurality of word lines maintained in the selected state, the voltage level of word line drive signal WLDV is raised to effect acceleration of voltage stress of a gate insulating film of memory cell transistors connected to word line WL.
When the test mode is completed, test mode instruction signal TM is inactivated and simultaneously test mode word line reset signal TM_WLRST is activated. In this way, WL reset circuit 502 is activated and word line reset timing signal WLOFF is activated. Responsively, level shifter 503 is reset, the word line drive timing signal is set into the inactive state of L level and word line drive signal WLDV is driven into L level. Word line reset signal WLRST from NOR circuit 505 reaches the active state of H level, reset transistors 509a and 509b are turned on and word lines WLi and WLi+1 (WL1, WL2) are driven into the non-selected state.
When the test mode is reset, test mode row decoder latch instruction signal TM_RDLTC is accordingly driven into the non-selected state, block decoder 500 is reset, block selection signal BLKSEL from level shifter 501 is set into the non-selected state of L level, and decode circuits 506a and 506b are inactivated.
In this test mode, block selection signal BLKSEL is fixed at H level so that row decode circuits 506a and 506b are not reset even if predecode signals XAij and XAkl change. At this time, a decoding operation is carried out and the result of the decoding is latched by latch circuits 507a and 507b merely, and a word line which is selected once maintains the selected state during this test mode.
An acceleration test is carried out with a plurality of word lines maintained in the selected state. Consequently, the time required for the acceleration test can remarkably be decreased compared with the case in which one word line is selected to perform the acceleration test.
FIG. 27 is a schematic diagram illustrating a structure of bit line peripheral circuitry of the semiconductor memory device disclosed in the document mentioned above. Referring to FIG. 27, for a pair of bit lines BL and ZBL, a bit line isolation gate 511 connecting bit lines BL and ZBL to a sense amplifier circuit (SA) 510 according to switch control signal MUX, a voltage selection circuit 513 selecting one of bit line equalize voltage VEQ and voltage from an output enable terminal (/G pin) according to test mode equalize instruction signals TMEQ and/TMEQ, and a bit line precharge circuit 512 transmitting the voltage from voltage selection circuit 513 to bit lines BL and ZBL according to an output signal of a bit line precharge control circuit 515 are provided.
A memory cell MC is arranged at the crossing of bit line BL and word line WL. Memory cell MC includes a capacitor Cm and an n channel MOS transistor Tm connecting capacitor Cm and bit line BL in response to the signal potential on word line WL.
Bit line precharge control circuit 515 receives test mode equalize instruction signal TM_SAEQ and bit line equalize instruction signal EQL and activates bit line precharge circuit 512 when one of those received signals is activated.
Bit line precharge circuit 512 includes MOS transistors Tc and Te which are turned on, when an output signal of bit line precharge control circuit 515 is activated, to transmit voltage from voltage selection circuit 513 to bit lines BL and ZBL respectively, and an n channel MOS transistor Td short-circuiting bit lines BL and ZBL.
Voltage selection circuit 513 includes a transfer gate Tg which becomes conductive, when test mode equalize instruction signal TMEQ is activated, to transmit voltage externally applied via the output enable terminal (/G pin), and a transfer gate Tf which becomes conductive, when test mode equalize instruction signal /TMEQ is inactivated, to transmit intermediate voltage VEQ from a bit line precharge voltage generating circuit (not shown).
For sense amplifier circuit (SA) 510, a p channel MOS transistor Tb and an n channel MOS transistor Ta which are turned on, in response to an output signal from sense amplifier control circuit 514, to transmit the power supply voltage and the ground voltage to sense amplifier circuit (SA) 510 are provided.
Sense amplifier control circuit 514 includes an NOR circuit 514a receiving inverted signal /SET of sense amplifier activation signal SET and test mode equalize instruction signal TMxe2x80x94SAEQ, and an inverter circuit 514b inverting an output signal of NOR circuit 514a. The output signal of NOR circuit 514a is supplied to a gate of n channel MOS transistor Ta, and the output signal of inverter circuit 514b is supplied to a gate of MOS transistor Tb.
An operation of the bit line peripheral circuitry shown in FIG. 27 is described below in conjunction with the signal waveform diagram shown in FIG. 28.
In a normal read/write mode in which a normal data access is made, word line WL is selected according to externally supplied row address strobe signal /RAS and an access (read or write) is made to a selected memory cell. At this time, test mode equalize instruction signals TMxe2x80x94SAEQ and TMEQ are in the inactive state of L level. Accordingly, voltage selection circuit 513 selects precharge voltage VEQ from the internal bit line precharge voltage generating circuit, and control circuits 514 and 515 control activation of sense amplifier 510 and activation of bit line precharge circuit 512, respectively, according to sense amplifier activation signal /SET and bit line equalize instruction signal EQL.
When a test mode starts, test mode instruction signal TM is activated, test mode equalize instruction signal TMEQ attains H level, and test mode equalize instruction signal TMxe2x80x94SAEQ is set at H level. Voltage selection circuit 513 selects external voltage applied externally via the output enable terminal (/G pin). Bit line precharge circuit 512 is activated in response to activation of an output signal of bit line precharge control circuit 515 and transmits the external voltage from voltage selection circuit 513 onto bit lines BL and ZBL. Sense amplifier circuit 510 is maintained in the inactive state according to an output signal of sense amplifier control circuit 514. The externally applied voltage is forced to stay at L level and multi-selection of word lines is carried out by utilizing the structure shown in FIG. 25. Thus, stress equal to the voltage on word line WL is applied to the gate insulating film of memory cell transistor Tm. Acceleration of the voltage stress on the gate insulating film of the memory cell transistor is accomplished.
In the structure shown in FIG. 25, all word lines WL are selected. In the structure in FIG. 27, test mode equalize instruction signals TMxe2x80x94SAEQ and TMEQ are set at H level and the voltage supplied from the output enable terminal (/G pin) is set at the ground voltage level. Accordingly, the voltage stress applied to the gate insulating films of all memory cell transistors can be accelerated simultaneously so that the time needed to effect the voltage stress acceleration of the gate insulating films can be decreased.
This burn-in test includes a test mode in which the voltage stress between adjacent memory cell capacitors is accelerated to reveal a potential defect of an interlayer insulating film between the adjacent memory cell capacitors.
FIG. 29A is a schematic view illustrating an arrangement of memory cells MC. FIG. 29A illustrates memory cells arranged at crossings of bit line pairs BL0, ZBL0 and BL1, ZBL1 and word lines WL0-WL8.
Memory cells MC are arranged periodically in a column direction with two memory cells MC being one unit. In a row direction (direction in which word lines extend), memory cell capacitors Cm are aligned with each other and bit line contacts BCT are aligned with each other in the row direction. In the column direction, between memory units each including two memory cells, there is an empty region corresponding to a word line pitch.
A sense amplifier circuit SA0 is associated with bit lines BL0 and ZBL0, and a sense amplifier circuit SA1 is associated with the pair of bit lines BL1 and ZBL1. Two memory cells MC are connected to a bit line via one bit line contact BCT, so that the number of contact regions decreases and accordingly the memory cells can be arranged highly densely.
FIG. 29B is a schematic cross sectional view showing a structure of the memory cell in FIG. 29A in the row direction. Referring to FIG. 29B, memory cell MC includes high concentration impurity regions 521b and 521c formed at the surface of a P type semiconductor substrate region 520, a storage node electrode 522b connected to impurity region 521b, a conductive layer 525 forming a bit line and connected to impurity region 521c, and a conductive layer 524 forming a word line and placed between impurity regions 521b and 521c with a gate insulating film (not shown) underlaid.
An adjacent memory cell includes a high concentration impurity region 521a isolated from impurity region 521b by a field insulating film 526, and a storage node electrode layer 522a connected to high concentration impurity region 521a. No transistor of the adjacent memory cell is shown.
A cell plate electrode layer 523 is formed commonly above storage node electrode layers 522a and 522b with a capacitor insulating film (not shown) interposed thereunder.
Suppose that the distance between storage node electrode layers 522a and 522b of the memory cell capacitors in the row direction is short as shown in FIG. 29B, and voltage stress is accelerated in order to reveal any potential defect of the interlayer insulating film between the storage node electrodes. In this case, it is required that data of L level, H level, L level and H level are written respectively into memory cell capacitors Cma, Cmb, Cmc and Cmd aligned in the row direction and the voltage level of the H level is raised. Specifically, bit lines BL0 and BL1 are set at H level, complementary bit lines ZBL0 and ZBL1 are set at L level, and all word lines are selected. In order to implement this operation, according to a normal operation mode, data of L level, H level, L level and H level are preliminary written into respective memory cell capacitors Cma, Cmb, Cmc and Cmd with the structure shown in FIGS. 25 and 27. When a test mode starts, it is then required that one word line is selected, a sense amplifier is activated, bit lines ZBL0 and ZBL1 are set at L level, bit lines BL0 and BL1 are set at H level, and thereafter word lines are successively driven into the selected state.
However, in order to write data into memory cell capacitors Cma-Cmd, an address should be designated externally to select the memory cell and write data into the selected memory cell. In order to select word lines successively, addresses should externally be designated successively in the structure shown in FIG. 25. Therefore, it is impossible to set all memory cells in the selected state at a high speed and a problem of increase of time period required for the burn-in (acceleration) test arises.
If the burn-in (acceleration) test is done after packaging, packaged memory devices are inserted into a plurality of sockets formed in a burn-in board and burn-in tests are performed simultaneously for a plurality of memory devices. In this case, if address signals are used to internally select word lines and memory cells successively, address signals should be applied to each board. A problem of shortage in number of pin terminals of a burn-in tester (aging device) then arises.
If the acceleration test is done at a wafer level, a tester contacts probes thereof with a plurality of dies (chips) on the wafer. In this case, address signals should be supplied in parallel to a plurality of dies (chips) and a problem of a considerable shortage in number of pins of the wafer burn-in tester arises.
The conventional structure shown in FIG. 25 in which all word lines are simultaneously driven into the selected state is accompanied by a problem that voltage stress on a contaminant particle between word lines cannot be accelerated.
An object of the present invention is to provide a semiconductor memory device capable of effecting a voltage stress acceleration test speedily and correctly with a small number of control signals.
Another object of the invention is to provide a semiconductor memory device capable of applying voltage stress between memory cell capacitors with a small number of control signals and in a short period of time.
Still another object of the invention is to provide a semiconductor memory device capable of accelerating voltage stress of short-circuit between word lines with a small number of control signals.
A further object of the invention is to provide a semiconductor memory device capable of driving a plurality of word lines simultaneously into selected state speedily with a small number of signals.
According to a first aspect of the present invention, a semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to the rows and each connected to memory cells of a corresponding row, a plurality of pairs of bit lines arranged corresponding to columns and each connected to memory cells of a corresponding column, a plurality of sense amplifier circuits arranged corresponding to the columns and activated to sense and amplify data in a memory cell on a corresponding column, a plurality of bit line precharge circuits arranged corresponding to the column and coupled to a reference voltage transmission line and each activated to transmit voltage on the reference voltage transmission line to a pair of bit lines of a corresponding column, and a test control circuit for activating each of the bit line precharge circuits and driving simultaneously into selected state a first predetermined number of word lines among a plurality of word lines in a first test mode operation, and inactivating a plurality of bit line precharge circuits, driving simultaneously into selected state a second predetermined number of word lines among a plurality of word lines and activating a plurality of sense amplifier circuits in a second test mode operation.
According to a second aspect of the present invention, a semiconductor memory device includes a plurality of memory blocks each having a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged corresponding to the rows and each connected to memory cells of a corresponding row, and a plurality of pairs of bit lines arranged corresponding to the columns and each connected to memory cells of a corresponding column, a plurality of groups of sense amplifiers including a plurality of sense amplifier circuits shared by memory blocks adjacent to each other in the column direction and, each corresponding to a column of a corresponding memory block and activated to sense and amplify data in a memory cell of a corresponding column, a plurality of bit line isolation circuits arranged between each group of sense amplifiers and a corresponding memory block and each activated to isolate a corresponding group of sense amplifiers from the corresponding memory block, a plurality of bit line precharge circuits arranged corresponding to the pairs of bit lines and shared by memory blocks adjacent to each other and connected to a reference voltage transmission line and each activated to transmit voltage on the reference voltage transmission line to a pair of bit lines of a corresponding column, and a test control circuit.
The test control circuit activates each bit line precharge circuit, inactivates a plurality of bit line isolation circuits, and drives simultaneously into selected state a first predetermined number of word lines among a plurality of word lines in each memory block in a first test mode operation, and inactivates a plurality of bit line precharge circuits, drives simultaneously into selected state a second predetermined number of word lines among a plurality of word lines in each memory block, and activates a plurality of sense amplifier circuits in a second test mode operation.
A bit line precharge circuit is activated and a plurality of word lines are selected simultaneously, so that data can be written into a memory cell by the voltages from the bit line precharge circuits and accordingly a column selecting operation becomes unnecessary.
Further, the bit line precharge circuits are inactivated, a plurality of word lines are simultaneously selected and a plurality of sense amplifiers are activated. As a result, the bit line voltage level can be set according to the data stored in a memory cell and the sense amplifier supply voltage can be changed to accelerate voltage stress between adjacent memory cell capacitors.
Geometrically alternate word lines are selected so that latent short-circuit between word lines can be revealed by voltage stress acceleration.
Further, an external control signal is used to generate an internal operation control signal and an internal address signal so that the number of signals supplied externally in the acceleration test can be decreased and accordingly the number of pins (the number of probes) of a burn-in tester (aging tester) can be decreased.